This invention relates to a circuit for outputting data to a digital level display unit in order to monitor a PCM level in a PCM recording and reproducing device or PCM reproducing device.
One example of a conventional digital level display unit for monitoring a PCM level, as shown in FIG. 8, comprises: a signal input terminal 1 to which a 16-bit PCM signal is applied; an absolute value conversion section 2 for converting the 16-bit PCM signal applied to the signal input terminal 1 into 15-bit absolute value data by ABSOLUTE-ORing the MSB (most significant bit) of the PCM signal and other bits; a peak latch section 3 for retaining the maximum value of the output data from the absolute value conversion section 2, the peak latch section 3 having a comparator 3a, a L-ch (left channel) register 3b, and a R-ch (right channel) register 3c; a data transferring register 4 for serially transferring 30-bit parallel data consisting of 15-bit peak data for left-channel and 15-bit peak data for right-channel; a CPU 5 operating according to a predetermined control program to perform, for instance, the logarithmic conversion of peak data, a display decoding operation for display, and a display driving operation; and a level display device 6 which is driven according to the result of the display decoding operation of the CPU 5.
In the digital level display unit thus organized, a 16-bit PCM signal applied to the signal input terminal 1 is converted into 15-bit absolute value data by the absolute value conversion section 2, the output of which is applied to the peak latch section 3. When the data applied to the peak latch section 3 is L-ch data, the peak latch section 3 causes the comparator 3a to compare the input data with the data which has been stored in the L-ch register 3b. When the input data is larger, the input data is stored in the L-ch register 3b. In the case where the maximum value data stored in the R-ch register 3c and the L-ch register 3b are applied to the CPU 5, first the data are transferred from the registers 3b and 3c to the data transferring register 4, and then the registers 3b and 3c are cleared by a clear signal. Next, the CPU 5 applies a data transferring clock signal to the data transferring register 4 so that the R-ch and L-ch maximum value data are applied, in a serial mode, to the CPU 5.
The CPU 5 uses the data provided by the data transferring register, to perform a logarithmic conversion operation according to the following equation (1) in which for the full scale data, 0 dB is selected; i.e., for the absolute value data the 15 bits of which are all "1", 0 dB is selected: ##EQU1## In order to turn on the display elements of the level display device 6, the CPU 5 decodes the data X obtained through the logarithmic conversion, to drive the level display device 6.
As is apparent rom the above description, the conventional circuit is disadvantageous in the following points: since the peak latch section 3 must process the data for every 15 bits, the scale of the circuit is unavoidably large. Furthermore, transferring the data to the CPU in a serial mode takes a relatively long period of time and requires multiple data lines. In addition, the CPU for processing the data must perform intricate arithmetic operations such as the above-described equation (1). Thus, the burden on the software is considerably large.